JEDEC JEP147-2003
Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA)

Standard No.

JEDEC JEP147-2003

Release Date

2003

Published By

(U.S.) Joint Electron Device Engineering Council Soild State Technology Association

Latest

JEDEC JEP147-2003

Scope

This procedure is intended for VNA (Vector Network Analyzer) based measurement of pin input capacitance for devices with SSTL (Stub Series Terminated Logic) interface . This procedure does not mandate a specific method for measuring input capacitance. It has only to be considered mandatory if it is explicitly refered to by a component specification in conjunction with a value of an input capacitance defined in such a specification.

JEDEC JEP147-2003 history

• 2003 JEDEC JEP147-2003 Procedure for Measuring Input Capacitance Using a Vector Network Analyzer (VNA)