This document specifies the application scenarios, system architecture, interface requirements, protocol layer, link layer, adaptation layer, physical layer, physical packaging requirements and testability requirements of chiplet interface bus technology. This document applies to CPUs, GPUs, artificial intelligence chips, network processors, network switching chips, etc., and can also be applied to other chips that apply small chip interface technology.
T/CESA 1248-2023 history
2023T/CESA 1248-2023 Technical requirement for chiplet interface bus