(U.S.) Joint Electron Device Engineering Council Soild State Technology Association
Scope
This document defines a constant voltage stress test procedure for characterizing time-dependent
dielectric breakdown or “wear-out” of thin gate dielectrics. The test is designed to obtain voltage
and temperature acceleration parameters required to estimate oxide life at use conditions. Unlike
highly accelerated ramp tests that are designed to be extremely fast and performed at the waferlevel,
the constant voltage test procedure may be conducted over long periods of time. It may be
applied at the wafer-level or with packaged devices.