(U.S.) Joint Electron Device Engineering Council Soild State Technology Association
Scope
In typical use, the on and off power cycles of functional devices will produce non-uniform temperature
distributions within package components as well as between the package and interconnected hardware
such as printed wiring boards (PWB), sockets, or heat sinks. The stresses that result from the temperature
gradients found in actual product may or may not be accurately simulated by use of isothermal
temperature cycling. This test method is a characterization tool which can augment and supplement
results obtained with the isothermal chamber-based temperature cycling described in both JESD22-A104
and JESD22-A105. It should be used as an alternative to JESD22-A104 or JESD22-A105 only if such
substitution can be technically justified. The test method uses a powered device, a thermal chip or an
external heat source to simulate temperature cycling effects on the component package and its materials,
including solder joints in free-standing and assembled configurations. Unlike either
JESD22-A104 or JESD22-A105, the power cycles described in this test method are intended to simulate
the range of usage conditions found from the vicinity of room ambient up to Tj maximum for the device,
and are not specifically intended as a highly accelerated test or to apply to harsh application conditions
such as those used to simulate some under-hood or aerospace environments.