IEC 62530:2007 (E)
IEC 62530 Ed. 1 (IEEE Std 1800(TM)-2005): Standard for SystemVerilog - Unified Hardware Design, Specification, and Verification Language

Standard No.

IEC 62530:2007 (E)

Release Date

2007

Published By

Institute of Electrical and Electronics Engineers (IEEE)

Scope

This standard provides a set of extensions to the IEEE 1364™ Verilog® hardware description language (HDL) to aid in the creation and verification of abstract architectural level models. It also includes design specification methods, embedded assertions language, testbench language including coverage and an assertions application programming interface (API), and a direct programming interface (DPI)...