JEDEC JESD82-6A.01-2023
DEFINITION OF THE SSTV32852 2.5 V 24-BIT TO 48-BIT SSTL_2 REGISTERED BUFFER FOR 1U STACKED DDR DIMM APPLICATIONS:

Standard No.

JEDEC JESD82-6A.01-2023

Release Date

2023

Published By

/

Scope

This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the 32852 24-bit to 48-bit SSTL_2 registered buffer for stacked DDR DIMM applications.